专用集成电路与系统国家重点实验室
讲座信息
题目：Run-time VLSI Performance Adaptation and Soft Error Measurement
报告人：Masanori Hashimoto (Osaka University)
时间：2013年3月19日（周二）14:00-15:00
地点：张江校区微电子楼369室
Abstract:
This talk consists of two parts; run-time adaptive performance control and soft error measurement and analysis. First I will present run-time adaptive performance control with on-chip sensors that predict timing errors. The sensors embedded into functional circuits capture delay variations due to not only die-to-die process variation but also random process variation, environmental fluctuation and aging. By compensating circuit performance according to the sensor outputs, we can overcome PVT worst-case design and reduce power dissipation while satisfying circuit performance. We applied the adaptive speed control to subthreshold circuits that are very sensitive to random variation and environmental fluctuation. Measurement results of a 65nm test chip show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding. Next, I will briefly introduce results of soft error measurement and analysis for subthreshold SRAM. As supply voltage becomes lower, critical charge, which is the charge to flip a bit, becomes smaller, which means SRAM becomes more susceptible to radiation. I will present measured soft error rates from 0.3V to 1.0V in 65nm for neutron and alpha particles, and discuss their trends.
Bio:
Masanori Hashimoto received the B.E., M.E. and Ph.D. degrees in Communications and Computer Engineering from Kyoto University, Kyoto, Japan, in 1997, 1999, and 2001, respectively. Since 2004, he has been an Associate Professor in Department of Information Systems Engineering, Osaka University. His research interest includes timing and power integrity analysis, ultra low power design, and design for variability and reliability. He served as TPC members for a number of conferences including DAC, ICCAD, ASP-DAC, ISPD, and DATE.
