Academics

VLSI Architectures for Low-Energy Machine Learning Systems

Published:2018-07-06 

Speaker: Prof. Keshab K. Parhi

Time and Date: 14:00 pm, July 06, 2018

Place: Room 206 of Genetics Building, Handan Campus, Fudan University

 

Abstract:

Reducing energy consumption of machine learning systems requires selection of discriminative features, selection of electrodes in multi-channel systems, and approximate computing based architectures for computing features and classifiers. In this talk, I will describe a new feature selection method referred as minimum-uncertainty sample elimination (MUSE) that can lead to selection of fewer features, and an incremental-precision based feature computation followed by multi-level classification. The proposed approach makes use of approximate computing and leads to an overall reduction in energy consumption.

 

Biography:

Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor and Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering. He has published over 600 papers, is the inventor of 29 patents, and has authored the textbook VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). His current research addresses VLSI architecture design of signal processing systems, hardware security, data-driven neuroscience and molecular computing. Dr. Parhi is the recipient of numerous awards including the 2017 Mac Van Valkenburg award and the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He was elected a Fellow of IEEE in 1996 and a Fellow of the AAAS in 2017.

 

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