CMOS circuit reliability and stochastic computational models

 

Speaker: Jie Han （University of Alberta and National Institute of Nanotechnology, Canada）            
Time and Date: 14:00-15:00, Dec. 27th, 2010
Place: Room 369, Microelectronics Building, Zhangjiang Campus

 

Abstract

As reliability becomes a major concern with the continuous scaling of CMOS technology, several computational methodologies have been developed for the reliability evaluation of logic circuits. Previous accurate analytical approaches, however, have a computational complexity that generally increases exponentially with the size of a circuit, making the evaluation of large circuits intractable. In this talk, novel computational models based on stochastic computation, in which probabilities are encoded in the statistics of random binary bit streams, are presented for the reliability evaluation of logic circuits. A computational approach using the stochastic computational models (SCMs) accurately determines the reliability of a circuit with its precision only limited by the random fluctuations inherent in the representation of random binary bit streams. The SCM approach has a linear computational complexity and is therefore scalable for use for any large circuits. Our simulation results demonstrate the accuracy and scalability of the SCM approach, and suggest its possible applications in VLSI design.

Biography

Jie Han received his BSc degree in electronic engineering from Tsinghua University in 1999, and his PhD degree from Delft University of Technology in 2004.
He was a NASA INAC (Institute for Nanoelectronics and Computing) Postdoctoral Fellow in the Department of Electrical and Computer Engineering at the University of Florida from 2004 to 2007. From 2007 to 2009, he worked as a Research Scientist at the Advanced Medical Diagnostics SA/BV in Belgium.
Dr. Han was named in the “Milestones of Science” for 2003 by the 125th anniversary issue of Science (July 1, 2005, Vol. 309, No. 5731), for developing theory of fault-tolerant nanocircuits. He was nominated for the 2006 Christiaan Huygens Price of Science by the Royal Dutch Academy of Science (Koninklijke Nederlandse Akademie van Wetenschappen (KNAW) Christiaan Huygens Wetenschapsprijs). He is a member of the Institute of Electrical and Electronics Engineers (IEEE), the Association for Computing Machinery (ACM), and the American Society for Engineering Education (ASEE).

Research interests

With the scaling of CMOS and emergence of other nanotechnologies, the random and statistical properties of devices start to challenge the traditional paradigm of deterministic computation. Circuits and systems built from nanoscale devices will have to deal with the inherent randomness and stochastic behaviour of the devices. To address these challenges, my research focuses on the design and modeling of probabilistic, energy-efficient and fault-tolerant circuits and systems based on nanoscale devices. It includes:
 • Developing models and tools that account for the variability and statistical properties of scaled CMOS and emerging nanotechnologies
 • Developing probabilistic/stochastic approaches that trade off accuracy for energy and explore the optimization of reliability, power and area of nanoscale circuits and systems
 • Devising probabilistic yet robust computational paradigms that leverage the statistical and stochastic characteristics of nanodevices.
 • I'm also interested in the computational modeling of biological systems including molecular, cellular, and genetic networks.