Where Should Programmable Hardware Go?

 ---- FPGAs as Systems vs. Embedded FPGAs in Systems

  

Jonathan Rose, University of Toronto

 

Time and Date: 10:00-11:30, March 6, 2013

Place: Room 369, Microelectronics Building, Zhangjiang Campus 

 

Abstract

As IC Fabrication processes shrink, the cost and risk of each single-chip fabrication increases dramatically with each new generation. This, together with the limits on power consumption of a single chip, has motivated the push towards more programmable systems using CPUs and GPUs. There seems to be a limit on the number of useful CPU cores, as well as GPU processors, so many companies are seeking the flexibility provided by programmable logic. In this talk I will present some of our measurements that show the area, speed and energy consumption of several applications on FPGAs, ASICs, CPUs and GPUs. As this heterogeneous world has arisen there are two approaches from an FPGA perspective: the FPGA vendors would like to make a super-chip, that contains all of the things that that customers will need. Alternatively, large SoC chip vendors and users would like to place an embedded FPGA core within a chip of their own specific design. I will describe a few of the vendor offerings, and discuss the issues related to embedded FPGA cores.

 

Biography

Professor Rose is from the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto. He received the Ph.D. degree in Electrical Engineering in 1986 from the University of Toronto. From 1986 to 1989, he was a Post-Doctoral Scholar and then Research Associate in the Computer Systems Laboratory at Stanford University. In 1989, he joined the faculty of the University of Toronto. He spent the 1995-1996 year as a Senior Research Scientist at Xilinx, in San Jose, CA, working on the Virtex FPGA architecture. From 1989 until 1999 he was an NSERC University Research Fellow.

  

In October 1998, he co-founded Right Track CAD Corporation, which delivered architecture for FPGAs and Packing, Placement and Routing software for FPGAs to FPGA device vendors. He was President and CEO of Right Track until May 1, 2000. Right Track was purchased by Altera, and became part of the Altera Toronto Technology Centre, where Rose was Senior Director until April 30, 2003. His group at Altera Toronto shared responsibility for the development of the architecture for the Altera Stratix, Stratix II, Stratix GX and Cyclone FPGAs. His group was also responsible for placement, routing, delay annotation software and benchmarking for these devices, and for the placement and routing software for the Altera Apex 20K and Flex 10K FPGAs. From May 1, 2003 to April 30, 2004 Rose held the part-time position of Senior Research Scientist at Altera Toronto. He has worked for Bell-Northern Research and a number of FPGA companies on a consulting basis.

  

He is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the Canadian Academy of Engineering, a Foreign Associate of the American National Academy of Engineering, and a Fellow of the Royal Society of Canada.