FSM Based Software Testing Apparatus

Speaker: Dr. Shir-Shen Chang (Synopsys)

Time and Date: 10:00-11:00, Mar. 20, 2013

Place: Room 369, Microelectronics Building, Zhangjiang Campus

Abstract

This talk covers a new testing system for a complex EDA implementation tool. The Finite State Machine (FSM) model is found to be an ideal way to represent the target software. The idea was fully realized into a software testing apparatus for everyday use. The talk will touch on the background of the software testing methodology, motivation of the new approach, examples of the application, and some results.

Biography

Shir-Shen works as an R&D Group Director of the Implementation Business Group at Synopsys, Inc.. Shir-Shen manages an international team with engineers in US and the Synopsys Shanghai IG R&D division, which has more than 100 engineers working on various R&D and product validation areas. Shir-Shen’s charters involve IC Compiler, Proteus, and Design Compiler. Currently, Shir-Shen’s technical interests are EDA software measurement and stability of QoR, performance, and quality. Besides R&D management work, Shir-Shen has been actively involved in many industrial standard development projects. Shir-Shen was credited with contributions in VHDL (IEEE-1076), DPCS (IEEE-1481), SDF (IEEE-1497), UPF (IEEE-1801), and DEF/LEF. Shir-Shen earned a Ph.D. degree in Electrical Engineering from Rensselaer Polytechnic Institute in 1989. Shir-Shen was also granted with three US patents in EDA modeling.