On-Chip Interconnection Network Designs Leveraging Emerging Technologies

Speaker: Dr. Yi Xu (AMD)

Time and Date: 9:30-10:15, Apr. 17, 2013

Place: Room 369, Microelectronics Building, Zhangjiang Campus

 

 

Abstract

Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and high-bandwidth fabric for interconnect design. The advent of the 3D technology and nanophotonics interconnects have provided opportunities to improve communication bandwidth, power and speed. However, the design of the 3D NoC topologies has important distinctions from 2D NoCs or off-chip interconnection networks, while nanophotonic networks have been challenged for their reliability due to several device-level limitations. One of the main issues is that fabrication errors (a.k.a. process variations) can cause devices to malfunction, rendering communication unreliable.

 

In this talk, I will talk about a low-diameter 3D network using low-radix routers firstly. The proposed network topology could reduce network latency by taking advantage of the start-of-the-art one-hop vertical communication design and utilize lateral long wires to shorten network paths. Next, I will introduce a series of methods to improve the reliability of optical network. The objective of the work is to maximize network bandwidth through proper arrangement among microrings and wavelengths with minimum power requirement. Each step is shown to improve bandwidth provisioning with lower power requirement.

 

 

Biography

Yi Xu is a researcher at AMD China Lab. She received her B.S. and M.S. in Microelectronics from Nanjing University, Ph.D in Electrical and Computer Engineering from the University of Pittsburgh. She is a member of the IEEE/ACM. Her research interests include efficient interconnection architecture design for 2D/ 3D Chip Multi-Processor (CMP), photonic network designs and cache coherence protocols.