Sustainable Silicon: Energy-Efficient, Self-Aware Microsystems

Speaker: Dr. Patrick Chiang (1000-Talents Professor at Fudan University)

Time and Date: 9:55- , Apr. 23, 2013

Place: Classroom 2102, Zhangjiang Campus

 

 

Abstract

Energy-efficiency and robustness are essential requirements for next-generation electronic systems, from exascale supercomputers to wearable vital-sign sensor bandages. In a conventional design, extraneous power is consumed in order to satisfy worst-case guard bands. In this talk, I will describe recent work at Oregon State, where on-chip adaptation and closed-loop feedback enables a self-adaptive system that can autonomously adapt its power and reliability, based on its operating environment.

 

Two major research thrusts are presented that illustrate this in situ self-adaptation:

 

1) Wireline Interconnects: Future many-core systems are limited not by the energy consumed to compute, but by the energy dissipated to communicate. First, I will describe high-speed serial links that demonstrate state-of-the-art energy efficiency (sub-0.5pJ/bit at 8Gbps, with Intel Circuits Research Lab, JSSC12-JSSC13), exploiting both circuit parallelism and digital calibration while operating in the near-threshold regime. Second, I will describe a robust 8Gbps, 1pJ/bit Ring-Resonator based CMOS Photonics Transceiver (with HP-Labs and Texas A&M, ISSCC13). Unreliable optical components are overcome by introducing resonator biasing/thermal tuning for the transmitter, while an adaptive receiver is designed that can tradeoff input sensitivity for power efficiency.

 

2) Disposable Sensor Bandage: The Holy Grail of non-invasive vital-sign monitoring is a sensor-on-a-chip so cheap/small/light that it can be embedded into a disposable battery-less patch. Hence, energy-efficiency is paramount, as is robustness due to the importance of the medical data. In this talk, I will discuss multiple near-threshold (NTV) prototypes that demonstrate both low power and resiliency for this sensor:

a) Parallel-SIMD biomedical processor with error resiliency [with UT-Austin, ISSCC12]

b) Sensor-on-a-chip with RF-harvesting efficiency tracking [CICC12 Best Paper Award]

 

 

Biography

Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007. He is an associate professor (on sabbatical) at Oregon State University. He currently is a 1000-Talents Young Professor at the ASIC & System State Key Laboratory at Fudan University in Shanghai, China.

 

Previously, he has worked at Datapath Systems (now LSI), Velio Communications (now Rambus), and Telegent Systems (now Spreadtrum), Tsinghua University, the Chinese Academy of Sciences, and Fudan University on various analog/mixed-signal microchips. Research sponsors include government (NSF, DOE, DARPA, USDA, AFRL), industry (Intel, LSI, HP-Labs, SRC, Trimble), and private foundations (Catalyst, Erkkila).

 

He is the recipient of a 2010 Department of Energy Early CAREER award and a 2012 NSF-CAREER award, for energy-efficient interconnects and robust near-threshold computing. He is an associate editor of the IEEE Transactions on Biomedical Circuits and Systems, and on the technical program committee for the IEEE Custom Integrated Circuits Conference. He has published 86 technical conference/journal papers, and has two Best Paper/Faculty awards. He currently leads a group of 10 PhD students/post-docs in energy-efficient circuits and systems, including near-threshold wireline transceivers, reliable silicon photonics, resiliency in near-threshold operation, and energy-constrained medical sensors.