The Fundamentals of RTN in Exploring the Dielectric and Reliabilities of Advanced CMOS Device s and Nonvolatile Memories

Speaker: Prof. Steve S. Chung (NCTU)

Time and Date: 15:00- , Dec. 23, 2013

Place: Room B213, Microelectronics Building, Handan Campus

 

 

Abstract

The ID-RTN (Drain Current Random Telegraph Noise) and Ig-RTN are believed to be the two most efficient techniques to study the generated traps inside the insulator, such as conventional SiO2, high-k gate dielectric, and the MIM structure of ReRAM devices. Basically, either method described a phenomenon where the carriers going into or going out of the generated oxide traps via carrier capture and emission. The oxide traps in the gate dielectric can be either in generic form (called process induced trap) or for the devices after the stress (called stress induced trap). A bunch of applications can be developed from the understanding of the measurement technique.

In this talk, first, the basics of Id Random Telegraph Noise (RTN) measurement technique will be introduced. Then, the applications to the understanding of gate dielectric and device reliability will be demonstrated for various types of CMOS devices after the 90nm generation, including the most recent interests in trigate CMOS from a 28nm generation node. The fundamentals of Ig-RTN will then be described which laid down the fundamental understanding of soft-breakdown. The applications of this Ig-RTN to the SONOS, Resistance RAM will then be introduced. Especially, the role of a newly observed RTN behavior which might lead to the failure of ReRAM will be addressed.

 

 

Biography

STEVE S. CHUNG received his Ph.D. degree from the University of Illinois at Urbana -Champaign, in Electrical Engineering. His Ph.D. thesis advisor is the world -famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.

Currently, he is a Chair Professor and UMC Research Chair Professor at the National Chiao Tung University (NCTU). Between 2007-2008, he was also the Dean of International Affairs at NCTU where he served since 1987. Between 2004 -2005, he was the first Department Head of EECS Honors Program, to promote a student exchange program with UC-Berkeley and UIUC. He was a Research Visiting Scholar with Stanford University in 2001, teaching classes at the University of California-Merced and Stanford university, from 2009-2010. He is also an Honorary Professor of the Institute of Microelectronics, the Chinese Academy of Sciences. He has been a consultant to the two world largest IC foundries, TSMC and UMC, on developing CMOS and flash memory technologies. His current research areas include Nanoscale CMOS devices, flash memory, interface characterization, and reliability modeling. He has more than 22 times presentations in IEDM and VLSI, in which 40 percent of the university papers (from Taiwan) presented at VLSI Technology Symposium was from his group.

He is an IEEE Fellow, EDS AdCom member (2004-2009, 2012 -2014), IEEE Distinguished Lecturer, and Editor of EDL(2002-2008), Regions/Chapters Chair of EDS(current) , ED Taipei chapter chair. He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, etc. He was awarded 3 times outstanding Research Award for excellence in research, and the current NSC Research Fellow, from the National Science Council. More recently, he was awarded the 2013 Pan Wen-Yuan outstanding research award to recognize the achievements of researcher in the Electronics among the Chinese society. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.